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rev. f information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. a lc 2 mos high speed 4- and 8-channel 8-bit adcs ad7824/ad7828 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? 2003 analog devices, inc. all rights reserved. functional block diagram rdy cs rd int db3 db2 db1 db0 db7 db6 db5 db4 three- state drivers 4-bit flash adc (4 lsb) v ref (+) 16 timing and control circuitry address latch decode ain1 ain4 ain8 mux * * ad7824 ?4-channel mux ** ad7828 ?8-channel mux a2 ?ad7828 only a0 a1 a2 ** v ref (+) v ref (? 4-bit flash adc (4 msb) 4-bit dac features 4 or 8 analog input channels built-in track-and-hold function 10 khz signal handling on each channel fast microprocessor interface single 5 v supply low power: 50 mw fast conversion rate: 2.5 s/channel tight error specification: 1/2 lsb general description the ad7824 and ad7828 are high speed, multichannel, 8-bit adcs with a choice of four (ad7824) or eight (ad7828) multi- plexed analog inputs. a half-flash conversion technique gives a fast conversion rate of 2.5 s per channel, and the parts have a built-in track-and-hold function capable of digitizing full-scale signals of 10 khz (157 mv/ s slew rate) on all channels. the ad7824 and ad7828 operate from a single 5 v supply and have an analog input range of 0 v to 5 v, using an external 5 v reference. microprocessor interfacing of the parts is simple, using standard chip select ( cs ) and read ( rd ) signals to initiate the conversion and read the data from the three-state data outputs. the half-flash conversion technique means that there is no need to generate a clock signal for the adc. the ad7824 and ad7828 can be interfaced easily to most popular microprocessors. the ad7824 and ad7828 are fabricated in an advanced, all ion-implanted, linear compatible cmos process (lc 2 mos) and have low power dissipation of 40 mw (typ). the ad7824 is available in a 0.3" wide, 24-lead ?kinny?dip, while the ad7828 is available in a 0.6" wide, 28-lead dip and in 28-terminal surface- mount packages. product highlights 1. 4- or 8-channel input multiplexer gives cost effective, space- saving multichannel adc system. 2. fast conversion rate of 2.5 s/channel features a per-channel sampling frequency of 100 khz for the ad7824 or 50 khz for the ad7828. 3. built-in track-and-hold function allows handling of four or eight channels up to 10 khz bandwidth (157 mv/ s slew rate). 4. tight total unadjusted error spec and channel-to-channel matching eliminate the need for user trims. 5. single 5 v supply simplifies system power requirements. 6. fast, easy-to-use digital interface allows connection to most popular microprocessors with minimal external components. no clock signal is required for the adc.
rev. f e2e ad7824/ad7828especifications (v dd = 5 v, v ref (+) = 5 v, v ref (e) = gnd = o v, unless otherwise noted. all specifications t min to t max , unless otherwise noted. specifications apply to mode 0.) parameter k version 1 l version b, t versions c, u versions unit conditions/comments accuracy resolution 8 8 8 8 bits total unadjusted error 2 1 1/2 1 1/2 lsb max minimum resolution for which no missing codes are guaranteed 8 8 8 8 bits channel-to-channel mismatch 1/4 1/4 1/4 1/4 lsb max reference input input resistance 1.0/4.0 1.0/4.0 1.0/4.0 1.0/4.0 k min/k max v ref (+) input voltage range v ref (e)/ v ref (e)/ v ref (e)/ v ref (e)/ v min/v max v dd v dd v dd v dd v ref (e) input voltage range gnd/ gnd/ gnd/ gnd/ v min/v max v ref (+) v ref (+) v ref (+) v ref (+) analog input input voltage range v ref (e)/ v ref (e)/ v ref (e)/ v ref (e)/ v min/v max v ref (+) v ref (+) v ref (+) v ref (+) input leakage current 3 3 3 3 a max analog input any channel input capacitance 3 45 45 45 45 pf typ 0 v to 5 v logic inputs rd , cs , a0, a1, and a2 v inh 2.4 2.4 2.4 2.4 v min v inl 0.8 0.8 0.8 0.8 v max i inh 111 1 a max i inl e1 e1 e1 e1 a max input capacitance 3 88 88 pf max typically 5 pf logic outputs db0edb7 and int v oh 4.0 4.0 4.0 4.0 v min i source = 360 a v ol 0.4 0.4 0.4 0.4 v max i sink = 1.6 ma i out (db0edb7) 3 3 3 3 a max floating state leakage output capacitance 3 88 88 pf max typically 5 pf rdy v ol 4 0.4 0.4 0.4 0.4 v max i sink = 2.6 ma i out 3 3 3 3 a max floating state leakage output capacitance 8 8 8 8 pf max typically 5 pf slew rate, tracking 3 0.7 0.7 0.7 0.7 v/ s typ 0.157 0.157 0.157 0.157 v/ s max power supply v dd 555 5 v 5% for specified performance i dd 5 16 16 20 20 ma max cs = rd = 2.4 v power dissipation 50 50 50 50 mw typ 80 80 100 100 mw max power supply sensitivity 1/4 1/4 1/4 1/4 lsb max 1/16 lsb typ v dd = 5 v 5% notes 1 temperature ranges are as follows: k, l versions: 0 c to 70 c b, c versions: e40 c to +85 c t, u versions: e55 c to +125 c 2 total unadjusted error includes offset, full-scale and linearity errors. 3 sample tested at 25 c by product assurance to ensure compliance. 4 rdy is an open-drain output. 5 see typical performance characteristics. specifications subject to change without notice.
ad7824/ad7828 rev. f e3e timing characteristics 1 (v dd = 5 v; v ref (+) = 5 v; v ref (e) = gnd = 0 v, unless otherwise noted.) limit at 25 c limit at t min , t max limit at t min , t max parameter (all grades) (k, l, b, c grades) (t, u grades) unit conditions/comments t css 00 0 ns min cs to rd setup time t csh 00 0 ns min cs to rd hold time t as 00 0 ns min multiplexer address setup time t ah 30 35 40 ns min multiplexer address hold time t rdy 2 40 60 60 ns max cs to rdy delay. pull-up resistor 5 k . t crd 2.0 2.4 2.8 s max conversion time, mode 0 t acc1 3 85 110 120 ns max data access time after rd t acc2 3 50 60 70 ns max data access time after int , mode 0 t lnth 2 40 65 70 ns typ rd to int delay 75 100 100 ns max t dh 4 60 70 70 ns max data hold time t p 500 500 600 ns min delay time between conversions t rd 60 80 80 ns min read pulsewidth, mode 1 600 500 400 ns max notes 1 sample tested at 25 c to ensure compliance. all input control signals are specified with t rise = t fall = 20 ns (10% to 90% of 5 v) and timed from a voltage level of 1.6 v. 2 c l = 50 pf. 3 measured with load circuits of figure 1 and defined as the time required for an output to cross 0.8 v or 2.4 v. 4 defined as the time required for the data lines to change 0.5 v when loaded with the circuits of figure 2. specifications subject to change without notice. t est circuits dbn 3k 100pf dgnd a. high-z to v oh dbn 3k 100pf dgnd 5v b. high-z to v ol figure 1. load circuits for data access time test dbn 3k 10pf dgnd a. v oh to high-z dbn 3k 10pf dgnd 5v b. v ol to high-z figure 2. load circuits for data hold time test
ad7824/ad7828 e4e rev. f operating temperature range commercial (k, l versions) . . . . . . . . . . . . . . 0 c to 70 c industrial (b, c versions) . . . . . . . . . . . . . e40 c to +85 c extended (t, u versions) . . . . . . . . . . . . e55 c to +125 c storage temperature range . . . . . . . . . . . . e65 c to +150 c lead temperature (soldering, 10 secs) . . . . . . . . . . . . 300 c power dissipation (any package) to 75 c . . . . . . . . . 450 mw derates above 75 c by . . . . . . . . . . . . . . . . . . . . . . 6 mw/ c * stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings * (t a = 25 c, unless otherwise noted.) v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 v, 7 v digital input voltage to gnd ( rd , cs , a0, a1, and a2) . . . . . . . . . e0.3 v, v dd + 0.3 v digital output voltage to gnd (db0, db7, rdy, and int ) . . . . . . . e0.3 v, v dd + 0.3 v v ref (+) to gnd . . . . . . . . . . . . . . . . . v ref (e), v dd + 0.3 v v ref (e) to gnd . . . . . . . . . . . . . . . . . . . . . . . . 0 v, v ref (+) analog input (any channel) . . . . . . . . . . e0.3 v, v dd + 0.3 v caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although ad7824/ad7828 feature proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. pin configurations dip/soic/ssop top view (not to scale) 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 ad7824 nc = no connect ain4 v dd ain3 nc ain2 a0 ain1 a1 nc db7 db0 db6 db1 db5 db2 db4 db3 cs rd rdy int v ref (+) gnd v ref (e) top view (not to scale) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ad7828 nc = no connect ain6 ain7 ain5 ain8 ain4 v dd ain3 a0 ain2 a1 ain1 a2 nc db7 db0 db6 db1 db5 db2 db4 db3 cs rd rdy int v ref (+) gnd v ref (e) warning! esd sensitive device plcc 25 24 23 22 21 20 19 5 6 7 8 9 10 11 4 3 2 1 28 27 26 pin 1 identifier top view (not to scale) 12 13 14 15 16 17 18 a0 ain2 v dd rd nc = no connect ad7828 a1 ain1 a2 nc db7 db0 db6 db1 db5 db2 db4 db3 ain8 ain7 ain6 ain5 ain4 ain3 int gnd v ref (e) v ref (+) rdy cs lccc top view (not to scale) 28 27 1 2 3 426 25 21 22 23 24 19 20 5 6 7 8 9 10 11 12 13 14 15 16 17 18 ad7828 ain2 a0 v dd rd ain1 a1 nc a2 db0 db7 db1 db6 db2 db5 db3 db4 ain8 ain7 ain6 ain5 ain4 ain3 int gnd v ref (e) v ref (+) rdy cs nc = no connect ordering guide total temperature unadjusted package model range error (lsbs) option ad7824kn 0 c to 70 c 1 n-24 ad7824ln 0 c to 70 c 1/2 n-24 ad7824kr 0 c to 70 c 1 r-24 ad7824bq e40 c to +85 c 1 q-24 ad7824cq e40 c to +85 c 1/2 q-24 AD7824TQ * e55 c to +125 c 1 q-24 ad7824uq * e55 c to +125 c 1/2 q-24 ad7828kn 0 c to 70 c 1 n-28 ad7828ln 0 c to 70 c 1/2 n-28 ad7828kp 0 c to 70 c 1 p-28a ad7828lp 0 c to 70 c 1/2 p-28a ad7828bq e40 c to +85 c 1 q-28 ad7828cq e40 c to +85 c 1/2 q-28 ad7828br e40 c to +85 c+ 1 r-28 ad7828lrs 0 c to 70 c 1/2 rs-28 ad7828tq * e55 c to +125 c 1 q-28 ad7828uq * e55 c to +125 c 1/2 q-28 ad7828te * e55 c to +125 c 1 e-28a ad7828ue * e55 c to +125 c 1/2 e-28a * available to /883b processing only. contact our local sales office for military data sheet. for u.s. standard military drawing (smd) see desc drawing #5692-88764.
t ypical performance characteristicsead7824/ad7828 rev. f e5e t a e ambient temperature e c 3 2 1 e100 150 e50 t crd e conversion time e s 050 100 v dd = 5v tpc 1. conversion time vs. temperature v ref e v 2.0 1.0 0 05 1 linearity error e lsb * 234 1.5 0.5 v dd = 5v t a = 25 c * 1lsb = v ref 256 tpc 2. accuracy vs. v ref [v ref = v ref (+) e v ref (e)] input frequency e khz e36 e44 e52 5 1 snr e db 234 e40 e48 e38 e46 e42 e50 20 30 40 50 70 100 710 encode rate = 400khz input signal = 5v p-p measurement bandwidth = 80khz tpc 3. signal noise ratio vs. input frequency t a e ambient temperature e c 14 12 10 e100 150 e50 i dd e supply current e ma 050 100 13 11 9 8 v dd = 5.25v v dd = 4.75v v dd = 5v tpc 4. power su pply current vs. temperature (not including reference ladder) t p e ns 2.0 1.0 0 300 linearity error e lsb 1.5 0.5 v dd = 5v v ref = 5v t a = 25 c 400 500 600 700 800 900 tpc 5. accuracy vs. t p t a e ambient temperature e c 8 4 e100 150 e50 output current e ma 050 100 10 6 2 0 i source , v out = 2.4v v dd = 5v i sink , v out = 0.4v tpc 6. output current vs. temperature
ad7824/ad7828 e6e rev. f operational diagram the ad7824 is a 4-channel 8-bit adc and the ad7828 is an 8-channel 8-bit adc. operational diagrams for both of these devices are shown in figures 3 and 4. the addition of just a 5 v reference allows the devices to perform the analog-to-digital function. 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 ad7824 nc = no connect ain4 v dd ain3 nc ain2 a0 ain1 a1 nc db7 db0 db6 db1 db5 db2 db4 db3 cs rd rdy int v ref (+) gnd v ref (e) analog inputs 0v to 5v p 4lsb data bus p control input status output p address bus p 4msb data bus p control input status output 5v 5v figure 3. ad7824 operational diagram 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ad7828 nc = no connect ain6 ain7 ain5 ain8 ain4 v dd ain3 a0 ain2 a1 ain1 a2 nc db7 db0 db6 db1 db5 db2 db4 db3 cs rd rdy int v ref (+) gnd v ref (e) analog inputs 0v to 5v p 4lsb data bus p control input status output analog inputs 0v to 5v p address bus p 4msb data bus p control input status output 5v 5v figure 4. ad7828 operational diagram circuit information basic description the ad7824/ad7828 uses a half-flash conversion technique whereby two 4-bit flash adcs are used to achieve an 8-bit result. each 4-bit flash adc contains 15 comparators that compare the unknown input to a reference ladder to get a 4-bit result. for a full 8-bit reading to be realized, the upper 4-bit flash, the most significant (ms) flash, performs a conversion to provide the four most significant data bits. an internal dac, driven by the four msbs, then recreates an analog approximation of the input voltage. this analog result is subtracted from the input, and the difference is converted by the lower flash adc, the least significant (ls) flash, to provide the four least significant bits of the output data. the most significant flash adc also has one additional comparator to detect overrange on the analog input. applying the ad7824/ad7828 reference and input the two reference inputs on the ad7824/ad7828 are fully differ- ential and define the zero to full-scale input range of the adc. as a result, the span of the analog input voltage for all channels can easily be varied. by reducing the reference span, v ref (+) to v ref (e), to less than 5 v, the sensitivity of the con verter can be increased (e.g., if v ref = 2 v then 1 lsb = 7.8 mv). the in put/ reference arrangement also facilitates ratiometric operation. this reference flexibility also allows the input channel voltage spa n to be offset from zero. the voltage at v ref (e) sets the i nput level for all channels, which produces a digital output of all zeroes. therefore, although the analog inputs are not them- selves differential, they have nearly differential input capability in most measurement applications because of the reference design. figures 5 to 7 show some of the configurations that are possible. ad7824 * ad7828 * ain1 gnd v dd v ref (+) v ref (e) 47 f 0.1 f v in (e) v in (+) 5v additional pins omitted for clarity. only channel 1 shown. * figure 5. power supply as reference ad7824 * ad7828 * ain1 gnd v dd v ref (+) v ref (e) 47 f 0.1 f v in (e) v in (+) 5v additional pins omitted for clarity. only channel 1 shown. * ad580 0.1 f 10 f figure 6. external reference using the ad580, full-scale input is 2.5 v ad7824 * ad7828 * ain1 gnd v dd v ref (+) v ref (e) 47 f 0.1 f v in (+) 5v additional pins omitted for clarity. only channel 1 shown. * db7 db0 data v1 v2 data = 256 (for all channels) v in (+) v1 e v2 figure 7. input not referenced to gnd
ad7824/ad7828 rev. f e7e input current due to the novel conversion techniques employed by the ad 7824/ ad7828, the analog input behaves somewhat differently than in conventional devices. the adc?s sampled-data comparators take varying amounts of input current depending on which cycle the conversion is in. the equivalent input circuit of the ad7824/ad7828 is shown in figure 8. when a conversion starts ( cs and rd going low), all input switches close, and the selected input channel is con- nected to the most significant and least significant comparators. therefore, the analog input is simultaneously connected to 31 input capacitors of 1 pf each. 1pf 1pf 15lsb comparators 1pf 1pf 16msb comparators to ls ladder r on r on r mux c s 12pf c s 2pf r s ain1 to ms ladder v in ad7824/ ad7828 figure 8. ad7824/ad7828 equivalent input circuit the input capacitors must charge to the input voltage through the on resistance of the analog switches (about 3 k to 6 k ). in a ddition, about 14 pf of input stray capacitance must be charged. t he analog input for any channel can be modelled as an rc network, as shown in figure 9. as r s increases, it takes longer for the input capacitance to charge. r on 350 r mux 800 c s1 12pf r s v in c s2 2pf 31pf ain1 figure 9. rc network model the time for which the input comparators track the analog input is approximately 1 s at the start of conversion. because of input transients on the analog inputs, it is recommended that a source impedance no greater than 100 be connected to the analog inputs. the output impedance of an op amp is equal to the open loop output impedance divided by the loop gain at the frequency of interest. it is important that the amplifier driving the ad7824/ ad7828 analog inputs have sufficient loop gain at the input signal frequency as to make the output impedance low. suitable op amps for driving the ad7824/ad7828 are the ad544 or ad644. inherent sample-hold a major benefit of the ad7824?s and ad7828?s analog input structure is its ability to measure a variety of high speed signals without the help of an external sample-and-hold. in a conven- tional sar type converter, regardless of its speed, the input must remain stable to at least 1/2 lsb throughout the conversion process if rated accuracy is to be maintained. consequently, for many high speed signals, this signal must be externally sampled and held stationary during the conversion. the ad7824/ad7828 input comparators, by nature of their input switching, inherently accomplish this sample-and-hold function. although the conver- sion time for ad7824/ad7828 is 2 s, the time for which any selected analog input must be 1/2 lsb stable is much smaller. the ad7824/ad7828 tracks the selected input channel for approximately 1 s after conversion start. the value of the analog input at that instant (1 s from conversion start) is the measured value. this value is then used in the least significant flash to generate the lower four bits of data. sinusoidal inputs the ad7824/ad7828 can measure input signals with slew rates as high as 157 mv/ s to the rated specifications. this means that the analog input frequency can be up to 10 khz without the aid of an external sample-and-hold. furthermore, the ad7828 can measure eight 10 khz signals without a sample-and-hold. the nyquist criterion requires that the sampling rate be twice the in put frequency (i.e., 2 10 khz). this requires an ideal anti- a liasing filter with an infinite roll-off. to ease the problem of a ntialiasing filter design, the sampling rate is usually much greater than the nyquist criterion. the maximum sampling rate (f max ) for the ad7824/ad7828 can be calculated as follows: f tt max crd p = + 1 f ee khz max = + = 1 26056 400 e.e t crd = ad7824/ad7828 conversion time t p = minimum delay between conversion t his permits a maximum sampling rate of 50 khz for each of the eight channels when using the ad7828 and 100 khz for each of the four channels when using the ad7824.
ad7824/ad7828 e8e rev. f unipolar operation the analog input range for any channel of the ad7824/ad7828 is 0 v to 5 v as shown in the unipolar operational diagram of figure 10. figure 11 shows the designed code transitions that occur midway between successive integer lsb values (i.e., 1/2 lsb, 3/2 lsb, 5/2 lsb, fs 3/2 lsbs). the output code is natural binary with 1 lsb = fs/256 = (5/256) v = 19.5 mv. ad7824 * ad7828 * ain1 gnd v dd v ref (+) v ref (e) 47 f 0.1 f v in 0v to 5v 5v additional pins omitted for clarity. only channel 1 shown. * db7 db0 v ref 5v figure 10. ad7824/ad7828 unipolar 0 v to 5 v operation 11111111 11111110 11111101 00000011 00000010 00000001 00000000 full-scale transition output code 1lsb 2lsb 3lsb fs e 1lsb fs 0 ain, input voltage e lsb 1lsb = fs 256 figure 11. ideal input/output transfer characteristic for unipolar 0 v to 5 v operation bipolar operation the circuit of figure 12 is designed for bipolar operation. an ad544 op amp conditions the signal input (v in ) so that only positive voltages appear at ain1. the closed loop transfer func- tion of the op amp for the resistor values shown is given below: ain v volts in 1 =? () 25 0625 .. the analog input range is 4 v and the lsb size is 31.25 mv. the output code is complementary offset binary. the ideal input/output characteristic is shown in figure 13. ad7824 * ad7828 * ain1 gnd v dd v ref (+) v ref (e) 47 f 0.1 f v in 5v additional pins omitted for clarity. only channel 1 shown. * db7 db0 5v ad544 5v 40k 27k 25k 12k figure 12. ad7824/ad7828 bipolar 4 v operation ain, input voltage e lsb 11111111 11111110 00000000 0v output code 01111111 01111110 00000010 00000001 10000001 10000000 10000010 11111101 +fs 2 efs 2 + 1lsb fs = 8v 1lsb = fs/256 figure 13. ideal input/output transfer characteristic for 4 v operation timing and control the ad7824/ad7828 has two digital inputs for timing and control. these are chip select ( cs ) and read ( rd ). a read operation brings cs and rd low, which starts a conversion on th e channel selected by the multiplexer address inputs (see table i). there are two modes of operation as outlined by the timing diagrams of figures 14 and 15. mode 0 is designed for m icroprocessors that can be driven into a wait state. a read operation (i.e., cs and rd are taken low) starts a con- version and data is read when conversion is complete. mode l does not require microprocessor wait states. a read operation initiates a con version and reads the previous conversion results. table i. truth table for input channel selection ad7824 ad7828 a1 a0 a2 a1 a0 channel 00 00 0 ain1 01 00 1 ain2 10 01 0 ain3 11 01 1 ain4 10 0 ain5 10 1 ain6 11 0 ain7 11 1 ain8
ad7824/ad7828 rev. f e9e mode 0 figure 14 shows the timing diagram for mode 0 operation. this mode can only be used for microprocessors that have a wait state facility, whereby a read instruction cycle can be ex tended to accommodate slow memory devices. a read operation brings cs and rd low, which starts a conversion. the analog multiplexer address inputs must remain valid while cs and rd are low. the data bus (db7edb0) remains in the three-state condition until conversion is complete. there are two converter status outputs on the ad7824/ad7828, interrupt ( int ) and ready (rdy), which can be used to drive the microprocessor ready/wait input. the rdy is an open-drain output (no internal pull-up device) that goes low on the falling edge of cs and goes high impedance at the end of conversion when the 8-bit conversion result appears on the data outputs. if the rdy status is not required, the external pull-up resistor can be omitted and the rdy output tied to gnd. the int goes low when conversion is complete and returns high on the rising edge of cs or rd . mode 1 mode 1 operation is designed for applications where the micropro- cessor is not forced into a wait state. a read operation takes cs and rd low, which triggers a conversion (see figure 15). the multiplexer address inputs are latched on the rising edge of rd . data from the previous conversion is read from the three-state data outputs (db7edb0). this data may be disregarded if not required. note that the rdy output (open drain output) does not provide any status information in this mode and must be con nected to gnd. at the end of conversion, int goes low. a second read operation is required to access the new conversion result. this read operation latches a new address into the multi- plexer inputs and starts another conversion. int returns high at the end of the second read operation, when cs or rd returns high. a delay of 2.5 s must be allowed between read operations. cs rd analog channel address rdy int data t css t as t rdy t crd t a cc2 t dh t inth t ah t as t p t css t csh address va l i d address va l i d data va l i d high impedance figure 14. mode 0 timing diagram cs rd analog channel address int data t css t as address va l i d old va l i d address va l i d new va l i d t csh t ah t rd t crd t inth t a cc1 t dh t a cc1 t dh t inth t ah t as t p t css t rd t csh figure 15. mode 1 timing diagram
ad7824/ad7828 e10e rev. f microprocessor interfacing the ad7824/ad7828 is designed to interface to microprocessors as read only memory (rom). analog channel selection, con- version start, and data read operations are controlled by cs , rd , and the channel address inputs. these signals are common to all memory peripheral devices. z80 microprocessor figure 16 shows a typical ad7824/ad7828ez80 interface. the ad7824/ad7828 is operating in mode 0. assume the adc is assigned a memory block starting at address c000. the follow- ing load instruction to any of the addresses listed in table ii will start a conversion of the selected channel and read the conversion result. ld b, (c000) at the beginning of the instruction cycle when the adc address is selected, rdy asserts the wait input so that the z80 is forced into a wait state. at the end of conversion, rdy returns high and the conversion result is placed in the b register of the microprocessor. data bus address bus address decode en 5v 5k a0 a1 a2 z80 ad7824 * ad7828 * a15 a0 mreq w ait rd d7 d0 cs rdy rd db7 db0 a0 a1 a2 ** linear circuitry omitted for clarity. for the ad7828 only ** * figure 16. ad7824/ad7828ez80 lnterface table ii. address channel selection ad7824 ad7828 address channel channel c000 1 1 c001 2 2 c002 3 3 c003 4 4 c004 5 c005 6 c006 7 c007 8 mc68000 microprocessor figure 17 shows an mc68000 interface. the ad7824/ad7828 is operating in mode 0. assume the adc is again assigned a memory block starting at address c000. a move instruction to any of the addresses in table ii starts a conversion and reads the conversion result. move b $c000, d0 once conversion has begun, the mc68000 inserts wait states until int goes low, asserting dtack at the end of conversion. the microprocessor then places the conversion results into the d0 register. data bus address bus address decode en 5v 5k a0 a1 a2 ad7824 * ad7828 * a23 a1 d7 d0 cs rdy rd db7 db0 a0 a1 a2 ** clr d ck q 7474 dtack r/ w as mc68000 linear circuitry omitted for clarity. for the ad7828 only ** * figure 17. ad7824/ad7828emc68000 interface tms32010 microcomputer a tms32010 interface is shown in figure 18. the ad7824/ ad7828 is operating in mode 1 (i.e., no p wait states). the adc is mapped at a port address. the following i/o instruction starts a conversion and reads the previous conversion result into the accumulator. in, a pa (pa = port address) the port address (000 to 111) selects the analog channel to be converted. when conversion is complete, a second i/o instruc- tion (in, a pa) reads the up-to-date data into the accumulator and starts another conversion. a delay of 2.5 s must be allowed between conversions. data bus a2 ** ad7824 * ad7828 * a1 a0 cs rd db7 db0 pa 2 pa 1 pa 0 men den d7 d0 tms32010 linear circuitry omitted for clarity. for the ad7828 only ** * figure 18. ad7824/ad7828etms32010 interface
ad7824/ad7828 rev. f e11e outline dimensions 24-lead plastic dual-in-line package [pdip] (n-24) dimensions shown in inches and (millimeters) 24 1 12 13 1.185 (30.01) 1.165 (29.59) 1.145 (29.08) 0.295 (7.49) 0.285 (7.24) 0.275 (6.99) 0.150 (3.81) 0.135 (3.43) 0.120 (3.05) 0.015 (0.38) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) seating plane 0.015 (0.38) min 0.180 (4.57) max 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.150 (3.81) 0.130 (3.30) 0.110 (2.79) 0.100 (2.54) bsc 0.060 (1.52) 0.050 (1.27) 0.045 (1.14) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design compliant to jedec standards mo-095ag b and-pass filter 1 b and-pass filter 2 b and-pass filter 7 b and-pass filter 8 amp speech input ain1 ain2 ain7 ain8 v dd v ref (e) v ref (+) 5v gnd 5v cs rd db7 db0 a2 a1 a0 data ad7828 figure 19. speech analysis using real-time filtering v dd gnd 5v cs rd ain1 ain2 ain3 ain4 v ref (+) v ref (e) ad7824 int db7 db0 a1 a0 wr db7 db0 a1 a0 v out a a gnd dgnd v out b v out c v out d ad7226 v ss v dd 15v v o 1 v o 2 v o 3 v o 4 sample pulse v ref 10v figure 20. 4-channel fast infinite sample-and-hold 28-lead plastic dual-in-line package [pdip] (n-28) dimensions shown in inches and (millimeters) 0.195 (4.95) 0.125 (3.18) 0.015 (0.381) 0.008 (0.204) 0.625 (15.87) 0.600 (15.24) 28 1 14 15 0.580 (14.73) 0.485 (12.32) 1.565 (39.7) 1.380 (35.1) seating plane 0.250 (6.35) max 0.022 (0.558) 0.014 (0.356) 0.200 (5.05) 0.115 (2.93) 0.015 (0.39) min 0.100 (2.54) bsc 0.70 (1.77) 0.30 (0.77) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design compliant to jedec standards ms-011ab
ad7824/ad7828 e12e rev. f outline dimensions 24-lead standard small outline package [soic] wide body (r-24) dimensions shown in millimeters and (inches) controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design compliant to jedec standards ms-013ad 0.32 (0.0126) 0.23 (0.0091) 8 0 0.75 (0.0295) 0.25 (0.0098) 45 1.27 (0.0500) 0.40 (0.0157) seating plane 0.30 (0.0118) 0.10 (0.0039) 0.51 (0.020) 0.33 (0.013) 2.65 (0.1043) 2.35 (0.0925) 1.27 (0.0500) bsc 24 13 12 1 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 15.60 (0.6142) 15.20 (0.5984) coplanarity 0.10 28-lead standard small outline package [soic] wide body (r-28) dimensions shown in millimeters and (inches) controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design compliant to jedec standards ms-013ae 0.32 (0.0126) 0.23 (0.0091) 8 0 0.75 (0.0295) 0.25 (0.0098) 45 1.27 (0.0500) 0.40 (0.0157) seating plane 0.30 (0.0118) 0.10 (0.0039) 0.51 (0.0201) 0.33 (0.0130) 2.65 (0.1043) 2.35 (0.0925) 1.27 (0.0500) bsc 28 15 14 1 18.10 (0.7126) 17.70 (0.6969) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) coplanarity 0.10
ad7824/ad7828 rev. f e13e outline dimensions 28-lead ceramic dip - glass hermetic seal [cerdip] (q-28) dimensions shown in inches and (millimeters) 28 114 15 0.610 (15.49) 0.500 (12.70) pin 1 0.005 (0.13) min 0.100 (2.54) max 15 0 0.620 (15.75) 0.590 (14.99) 0.018 (0.46) 0.008 (0.20) seating plane 0.225(5.72) max 1.490 (37.85) max 0.150 (3.81) min 0.200 (5.08) 0.125 (3.18) 0.015 (0.38) min 0.026 (0.66) 0.014 (0.36) 0.100 (2.54) bsc 0.070 (1.78) 0.030 (0.76) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design 24-lead ceramic dip - glass hermetic seal [cerdip] (q-24) dimensions shown in inches and (millimeters) 24 112 13 0.310 (7.87) 0.220 (5.59) pin 1 0.005 (0.13) min 0.098 (2.49) max 15 0 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) seating plane 0.200 (5.08) max 1.280 (32.51) max 0.150 (3.81) min 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.100 (2.54) bsc 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design 28-terminal ceramic leaded chip carrier [lcc] (e-28a) dimensions shown in inches and (millimeters) 1 28 5 11 18 bottom view 19 25 26 4 12 0.15 (3.81) ref 0.075 (1.91) ref 0.028 (0.71) 0.022 (0.56) 0.300 (7.62) ref 0.055 (1.40) 0.045 (1.14) 0.075 (1.91) ref 0.020 (0.51) min 0.05 (1.27) bsc 0.095 (2.41) 0.075 (1.90) 0.458 (11.63) 0.442 (11.23) sq 0.458 (11.63) max sq 0.100 (2.54) 0.064 (1.63) 0.088 (2.24) 0.054 (1.37) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design
ad7824/ad7828 e14e rev. f outline dimensions 28-lead plastic leaded chip carrier [plcc] (p-28a) dimensions shown in inches and (millimeters) 4 5 26 25 11 12 19 18 top view (pins down) sq 0.456 (11.582) 0.450 (11.430) 0.050 (1.27) bsc 0.048 (1.22) 0.042 (1.07) 0.048 (1.22) 0.042 (1.07) 0.495 (12.57) 0.485 (12.32) sq 0.021 (0.53) 0.013 (0.33) 0.430 (10.9) 0.390 (9.9) 0.032 (0.81) 0.026 (0.66) 0.120 (3.05) 0.090 (2.29) 0.056 (1.42) 0.042 (1.07) 0.020 (0.51) min 0.180 (4.57) 0.165 (4.19) bottom view (pins up) 0.040 (1.02) 0.025 (0.64) compliant to jedec standards mo-047ab controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design 28-lead shrink small outline package [ssop] (rs-28) dimensions shown in millimeters 0.25 0.09 0.95 0.75 0.55 8 4 0 0.05 min 1.85 1.75 1.65 2.00 max 0.38 0.22 seating plane 0.65 bsc 0.10 coplanarity 28 15 14 1 10.50 10.20 9.90 5.60 5.30 5.00 8.20 7.80 7.40 compliant to jedec standards mo-150ah
ad7824/ad7828 rev. f ?5 revision history location page 1/03 ?ata sheet changed from rev. e to rev. f. edits to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 edits to dip/soic/ssop, lccc, and plcc pin configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 edit to figure 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 edits to circuit information basic description section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 edits to input current section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 edit to figure 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 edit to figure 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4/02?ata sheet changed from rev. d to rev. e. edits to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
c01323e0e1/03 (f) printed in u.s.a. e16e

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